1. Field of the Invention
The invention relates to a vertical transistor, a memory arrangement and a method for fabricating a vertical transistor.
2. Description of the Related Prior Art
In view of rapid ongoing development of computer technology, there is a need for storage media which provide ever greater storage quantities on ever smaller arrangements. Usually, larger quantities of data are stored in a large arrangement of memory cells. Memory cells used are, by way of example, nonvolatile memories which can store a stored item of information for a long period of time without loss of information. By way of example, transistors on silicon chips are used as nonvolatile memories.
However, as miniaturization advances further, conventional silicon microelectronics will encounter its limits. In particular, the development of increasingly smaller and more densely arranged transistors of, in the meantime, several hundred million transistors per chip will be subject to fundamental physical problems in the next ten years. In the event of the structural dimensions falling below 80 nm, quantum effects will have a disturbing influence on the components situated on the chips, and will predominate below dimensions of about 30 nm.
The increasing integration density of the components on the chips also leads to undesirable crosstalk between the components situated on the chips and to a dramatic increase in the waste heat. Therefore, increasing the storage density of transistor arrangements by means of advancing miniaturization of the transistor dimensions is a concept which will encounter physical limits in the foreseeable future.
Therefore, concepts with alternatives to the progressive miniaturization of the dimensions of individual transistors are being pursued. One concept which is being pursued for the purpose of further increasing the storage density is based on the basic idea of integrating transistors vertically instead of in planar fashion in the chips.
In this case, vertical transistors can be fabricated with physically required dimensions that are controllable in terms of production engineering, with increased packing density, in transistor arrangements. Especially nonvolatile memory cells using flash technology with gate oxides are often formed as vertical transistors since these memory cells require certain thicknesses for the gate oxides. This is due to the fact that tunnel effects using high voltages are utilized for programming or erasing the memory cells. Moreover, during fabrication vertical transistors afford the possibility of a freely selectable channel length, thereby making it possible to avoid the breakdown effects which occur in the case of space-reduced planar transistors.
However, in the case of the previously known concepts for vertical transistors, only the planar transistor structures are fabricated essentially vertically in the chips. Fabrication methods which are complicated and time-intensive thus result for the known vertical transistors. This is primarily due to the fact that the channel length must be sufficiently large in order to avoid breakdown effects between the two transistor main electrodes xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d. This consequently also requires a sufficiently large area for the transistor control electrode xe2x80x9cgatexe2x80x9d, in order to be able to reliably control the charge carrier channel that forms between source and drain.
Consequently, the invention is based on the problem of providing a vertical transistor, a memory arrangement and a method for fabricating a vertical transistor in which the machine and temporal outlay for the fabrication thereof is reduced.
The problem is solved by means of a vertical transistor, a memory arrangement and a method for fabricating a vertical transistor having the features in accordance with the independent patent claims.
A vertical transistor has a source region, a drain region, a gate region, and a channel region between the source region and the drain region. The source region, the channel region and the drain region are arranged in a vertical direction in a semiconductor substrate. The gate region has an electrical insulation from the source region, from the drain region and from the channel region. The gate region is arranged around the channel region in such a way that the gate region and the channel region form a coaxial structure.
A memory arrangement has a plurality of vertical transistors according to the invention, the vertical transistors being arranged next to one another in a memory matrix in the semiconductor substrate.
In a method for fabricating a vertical transistor, firstly a first electrically conductive region is produced on a semiconductor substrate. A channel region is then produced above the first electrically conductive region. Afterward, firstly an insulation layer and then a gate region are produced around the channel region in such a way that on the one hand, the channel region, the insulation layer and the gate region form a coaxial structure, and that on the other hand the gate region is electrically insulated from the first electrically conductive region. Finally, a second electrically conductive region is produced above the channel region, and is electrically insulated from the gate region.
One advantage of the invention can be seen in the fact that the problem of the time-intensive fabrication method is reduced by reducing the volume required for the vertical transistor according to the invention in the chip. This is achieved by virtue of the fact that, on account of the coaxial structure of the channel region and of the gate region, a large gate area is created despite a reduced channel length.
A further advantage of the invention is that the fabrication outlay is reduced on account of the coaxial structure, since the coaxial structure can be fabricated by means of symmetrical processes and masks. By way of example, the coaxial structure can be fabricated by means of selective deposition methods, selective etching methods and other self-aligning methods. This means that part of the fabrication process can be obviated, which results in a significant reduction of the process costs.
The coaxial structure of the vertical transistor according to the invention affords the advantage of a reduced space requirement of the vertical transistor in the directions parallel to the surface of the semiconductor substrate. As a result, an increased packing density can be achieved in a memory arrangement having a plurality of vertical transistors according to the invention. Consequently, future memory modules based on a memory arrangement having a plurality of vertical transistors according to the invention will be able to store a quantity of data of up to one Gbit.
In the case of the vertical transistor according to the invention, a charge carrier channel which can be formed between the source region and the drain region in the channel region can be coaxially constricted by means of an electric potential which can be applied to the gate region. This has the advantage of exact controllability of the position of the charge carrier channel and of charge carriers transferred in the charge carrier channel, and thus of the current flowing in the charge carrier channel. Moreover, the coaxial structure ensures reliable control of the charge carrier channel arranged between the source region and the drain region on account of a coaxial constriction. Undesirable charge carrier breakdowns between the source region and the drain region can thus be avoided.
In accordance with one exemplary embodiment of the vertical transistor according to the invention, the electrical insulation between channel region and gate region has a layer sequence comprising electrically insulating layers. The layer sequence preferably has a central layer bounded by two edge layers. In this case, the central layer is provided for storing electrical charge carriers. In this case, the electrical insulation is preferably an oxide-nitride-oxide layer sequence comprising a first oxide layer, a nitride layer and a second oxide layer.
Preferably, electrical charge carriers can be stored in a region of the central layer of the electrical insulation between the channel region and the gate region. In the case of an oxide-nitride-oxide layer sequence, the electrical charge carriers can then be stored in a region of the nitride layer.
In a preferred embodiment of the method according to the invention, a layer sequence comprising electrically insulating layers is produced as insulation layer between the channel region and the gate region. Preferably, electrical charge carriers are stored in a region of the insulation layer between the channel region and the gate region.
In a preferred development of the method according to the invention, a charge carrier channel is formed between the first electrically conductive region and the second electrically conductive region in the channel region, and can be coaxially constricted by means of an electric potential which can be applied to the gate region.
An oxide-nitride-oxide layer sequence comprising a first oxide layer, a nitride layer and a second oxide layer is produced as insulation layer between the channel region and the gate region. Electrical charge carriers are then stored in a region of the nitride layer between the channel region and the gate region.
An exemplary embodiment of the invention is illustrated in the figures and is explained in more detail below. In this case, identical reference signs designate identical components.